STM32G474 ADC After Idle: Apply the First-Conversion Workaround to the Correct Silicon Revisions

For affected STM32G474 silicon, the first ADC conversion after a sufficiently long idle interval can be incorrect. The documented workaround is a pair of consecutive conversions: discard the first result and retain the second. Applying that rule only once at boot misses the same condition after later slow polling or inactivity.

This article is limited to ES0430 Rev 9, section 2.7.9, using one regular ADC input channel. The erratum states the condition as a conversion occurring more than one millisecond after the previous conversion or ADC calibration. It does not disclose an internal analog root cause, and none is assumed here.

Identify the revision before applying the rule

Table 2 maps silicon revision markings Z, Y and X to REV_ID values 0x2001, 0x2002 and 0x2003, respectively. Table 3 marks section 2.7.9 as present with an available workaround on all three revisions.

Record the exact orderable part, silicon revision and errata revision with the acquisition configuration. A family name alone is insufficient evidence for another G4 device. Conversely, changing from revision Z to X does not remove this particular limitation according to the cited matrix.

The matrix also prevents confusion with nearby limitations whose affected revisions differ. The ADC chapter contains several superficially similar first-result and channel-sequence problems. Use the section number and trigger condition as the key, rather than a remembered instruction to “discard a sample.”

Pair conversions at each affected acquisition

Consider an original slow-monitoring fixture. Calibration completes at time zero. The application requests a reading at five milliseconds and another at ten milliseconds. The long gaps are chosen to make the documented idle condition obvious; they are not measured board timestamps.

At the first request, conversion A is the first conversion after the long gap. Its result is discarded. Conversion B follows consecutively on the same regular channel, and B supplies the application reading. At the second request, the elapsed gap again requires the same treatment: discard C and retain the consecutive D result.

calibration at 0 ms
request at 5 ms:  A [discard] -> B [retain]
request at 10 ms: C [discard] -> D [retain]

The arrows mean the documented consecutive acquisition sequence. They are not permission to schedule the second conversion at the next five-millisecond polling tick. If A and B are separated by another long idle interval, B is itself exposed to the condition that the pair was meant to avoid.

Each slow polling request uses a consecutive ADC pair, discarding the first result and retaining the second; the same rule is repeated after the next long idle gap.
Original discard-order fixture for the specific idle-conversion erratum. No hardware samples were collected.

For a real implementation, verify how the selected driver or DMA layout represents both results. A two-element buffer is useful only if the consumer keeps the correct element from the intended pair. Do not average A and B, publish A early, or let a later callback relabel A as the retained sample.

Avoid the adjacent erratum’s opposite discard order

Section 2.7.8 concerns ADC input-channel switching disturbing ongoing conversions. Its scan-mode workaround performs successive conversions on each input but keeps the first and discards the second. Its single-channel workaround is different again.

That is the opposite discard order from section 2.7.9. Copying the scan instruction from the preceding paragraph into this idle-recovery path preserves exactly the result that section 2.7.9 tells software to reject.

The two entries have different conditions and applicability. A design that also triggers channel-switch disturbance needs a combined review of both conditions; this single-channel idle fixture does not claim one pair resolves every ADC erratum.

Verify selection without manufacturing an accuracy claim

A proposed software test can label successive simulated results A, B, C and D and check that only B and D reach the consumer. Also test the mistaken one-time startup discard and the mistaken reversed discard order. These tests establish sequence handling, not the magnitude or probability of the silicon error.

A later controlled board check should preserve the revision identity, time since calibration or the preceding conversion, pair timing and retained-result index. Breakpoints and slow debug polling can create an idle interval, so record them as possible fixture conditions rather than treating a debug session as ordinary continuous acquisition.

No conversions were executed here. The acceptance question is whether every acquisition exposed to the cited idle condition uses the documented consecutive pair and rejects its first result. Other input-range, settling, timing and accuracy requirements remain separate; a correctly selected second result is not a complete ADC accuracy certification.

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