STM32G474 FDCAN Transmit Order: Choose FIFO Arrival Order or Queue Identifier Priority

A low numerical CAN identifier cannot win arbitration while it remains behind another frame in the controller’s local transmit FIFO. The STM32G474 offers a configuration choice that changes which pending entry becomes the node’s transmission candidate. That choice precedes competition with other nodes on the bus.

This explanation uses RM0440 Rev 9, March 2025, section 44.3.6 and the FDCAN_TXBC and FDCAN_TXFQS descriptions. Its schedule is a constructed example, not a captured CAN trace. It remains within the G474 integration’s three transmit entries.

Name the two scheduling boundaries

The local transmit handler selects among requests already pending in this FDCAN instance. Bus arbitration subsequently concerns the frames that participating nodes actually present. A high-priority frame waiting in application memory has not entered either decision; a frame waiting behind a local FIFO head has not displaced that head.

Use separate trace fields for application enqueue, controller request, local selection and observed bus transmission. Without those distinctions, a latency report can blame bus load for a delay introduced before the frame became a bus contender.

An already ongoing frame is another boundary. Changing the set of waiting requests does not turn the following paper example into a promise that a later frame interrupts a transmission already underway. Establish the pending set and selection instant before interpreting order.

Compare the same pending set in both modes

Clearing FDCAN_TXBC.TFQM selects FIFO operation. The handler starts with the entry identified by FDCAN_TXFQS.TFGI and advances the get index cyclically as transmissions complete. Setting TFQM selects queue operation, which chooses the pending message with the lowest message ID.

Assume three standard-identifier frames are made pending before the first selection, occupy entries in arrival order, and experience no cancellation, new arrival or transmission error. The identifiers are deliberately asymmetric:

arrival order:       0x500, 0x100, 0x300
FIFO candidate order: 0x500, 0x100, 0x300
Queue candidate order: 0x100, 0x300, 0x500

These are local candidate sequences under the stated conditions. Other nodes may still win the bus, and their traffic can change elapsed time without changing the explanation of local selection. The comparison therefore establishes an ordering policy, not a latency bound.

Choose the policy from the protocol requirement. If different identifiers must retain producer arrival order, a priority queue changes that contract. If an urgent low-ID frame must be considered ahead of older higher-ID entries, FIFO ordering can introduce avoidable local waiting. Neither choice manufactures spare buffering capacity.

Preserve the identifier comparison rules

For mixed standard and extended identifiers, the manual compares a standard ID with bits 28:18 of an extended ID. Comparing their raw integer values as though they had the same width can therefore model the wrong priority relationship.

For equal message IDs in multiple queue buffers, the documented tie-break is the lowest buffer number. That is not a general oldest-message guarantee. After entries have been reused, buffer number and producer arrival time need not describe the same ordering. Keep the main fixture all-standard with distinct IDs, then add separate mixed-format and equal-ID cases if the product uses them.

The queue’s put index answers where a new entry can be placed, not which pending entry will transmit first. When FDCAN_TXFQS.TFQF indicates a full queue, that put index is invalid. A plausible-looking index must not authorize overwriting an entry whose request remains pending.

Read the erratum without enlarging the hardware

ES0430 Rev 9, section 2.19.2 describes FIFO inversion under a specific combination of dedicated-buffer use, FIFO use and higher internal priority in the dedicated buffer. Its applicability must be checked against the actual silicon revision and configuration.

This is a qualified erratum, not the ordinary queue-selection rule. The three-entry fixture above uses only the FIFO or only the queue. Do not copy the erratum’s generic buffer-4/buffer-5 workaround into this G474 layout: those example numbers do not create additional transmit entries. Resolve any proposed mixed-buffer arrangement against the actual register and memory-map constraints first.

Specify an inert acceptance trace

For a later isolated bench check, arrange the same pending set before allowing its selection and preserve the request order, entry numbers, identifier format and configured mode. Use benign frames on a controlled CAN network, with no operational actuators. No such test was executed here.

Inspect the mode and status alongside the capture. Include one case with an entry already transmitting, so the report cannot confuse pending-priority selection with preemption. If an observed order differs, investigate request timing, full-state handling, cancellation, errors and applicable errata before changing identifiers.

The useful design record explains which frame was eligible for local selection and which frame ultimately appeared on the bus. Keeping those answers separate makes transmit ordering a reviewable policy rather than a guess based on numerical CAN priority alone.