RISC-V Sv39 Boot Mappings: Distinguish a Bad Virtual Address from a Misaligned Superpage
An RV64 supervisor faults immediately after enabling translation.
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ESP32-S3 PSRAM Integration Must Preserve Buffer Capabilities When Resizing
Trace ordinary realloc through ESP-IDF v5.2.5 before allowing a library to resize internal buffers, and preserve capability requirements across success and failure.
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RISC-V Debug Memory Dumps: Stop the Last SBA Read from Fetching One Word Too Far
A debugger requests three words from a RISC-V target but the bus trace shows four reads.
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ESP32-S3 USB Product Design Needs a PHY Map and an Independent Recovery Route
Separate ESP32-S3 USB controllers, runtime PHY selection and ROM download policy before choosing a product connector and recovery path.
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RISC-V Debug Register Reads: Recover the Abstract Command State Before Retrying
A debugger reads one CPU register successfully, encounters an unsupported CSR, and then reports that every later register read failed.
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STM32CubeIDE Exception Traps Must Agree with Standalone Firmware
A deliberately faulty operation stops cleanly in STM32CubeIDE, yet the same firmware behaves differently after a cold start without the debugger.
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STM32WB55 Low Power Requester Bits Are Not Reference Counted Locks
Treat STM32WB55 low-power requester bits as owned vetoes rather than reference-counted locks when asynchronous operations overlap.
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STM32CubeIDE 2.x Handover Must Separate Building from CubeMX Generation
A receiver installs STM32CubeIDE 2.x, imports a delivered project, and cannot follow an old instruction to edit the pin configuration inside the IDE.
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STM32WB55 Radio Stalls Capture CPU2 Fault Evidence Before Reset
Capture STM32WB55 CPU2 fault markers and register evidence before reset erases the distinction between a radio fault and a CPU1 dispatch failure.
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STM32CubeIDE Attach Sessions Must Not Download Away the Failure
A board reaches an intermittent failure, an engineer starts debugging, and the failure disappears before the first register is inspected.
