Cortex-M4F Lazy FPU Stacking: Budget the First Floating-Point Instruction in an ISR
An interrupt can enter promptly yet encounter deferred floating-point context-saving work later, at its first FPU instruction. Measuring only the first GPIO transition inside the handler can miss that cost. Qualify the complete deadline-critical path under both floating-point-active and inactive interrupted contexts. This guide concerns Cortex-M4 processors with the optional FPU, commonly called Cortex-M4F, using…