STM32G474 ADC Auto-Delay: Explain Why Unread Results Make Hardware Triggers Disappear
With AUTDLY enabled, an unread STM32G474 regular ADC result can prevent subsequent hardware triggers from starting conversions. Reading the result releases the delay, but it does not replay the triggers that arrived while admission was blocked. A clean data register can therefore coexist with gaps in the intended sampling schedule.
The scope here is one regular channel, externally triggered, with continuous conversion disabled and no injected or auto-injected activity. RM0440 Rev 9, section 21.4.27, pages 642–643 defines the behavior. The timeline is an original timing model, not an ADC capture.
Identify what ends the automatic delay
ADC_CFGR.AUTDLY allows the next regular conversion only after software has read ADC_DR or cleared EOC. The delay follows each regular conversion. It adapts acquisition progress to result consumption and can avoid overwriting data that a slow consumer has not treated.
For the selected hardware-triggered mode, a regular trigger during the ongoing regular sequence or the following automatic delay is ignored. The specification does not describe that ignored event as a request waiting in a FIFO. Do not borrow pending-trigger behavior from a different group or mode to fill the missing sample later.
This distinction changes the meaning of a sample counter. Counting result reads records conversions actually obtained. Counting timer triggers records requested opportunities. Neither counter alone proves a one-to-one mapping between trigger times and returned results.
Walk through a delayed read
Assume illustrative trigger times of 0, 10, 20 and 30 microseconds, and a modeled conversion duration of two microseconds. These numbers are chosen only to separate events; an implementation must derive legal timings from its ADC clock and sampling configuration.
- At 0 microseconds, the first trigger is admitted.
- At 2 microseconds, the result becomes available and the automatic delay begins.
- At 10 and 20 microseconds, the next triggers arrive while the result remains untreated. Both are ignored.
- At 25 microseconds, software reads
ADC_DR. The delay ends. - At 30 microseconds, the next hardware trigger starts a new conversion.
There is no conversion starting at 25 microseconds merely to compensate for the two missing triggers in this selected mode. The newly opened admission opportunity waits for the next valid trigger. A measurement timestamp assigned from the read time would also hide when the retained sample was actually acquired.
If software instead consumes the first result before the 10-microsecond trigger, that next trigger can be admitted, provided all other timing requirements are met. The relevant budget includes conversion completion and result-consumption latency, with margin for the asynchronous boundary. A nominal average interrupt latency is insufficient to establish the worst case.
Choose whether backpressure is acceptable
For a slow monitor whose requirement is to retain each completed conversion until consumed, automatic delay can be useful. Its acquisition cadence follows the consumer’s ability to release the previous result. The application should expose the actual sample timing rather than promise every periodic trigger was honored.
A fixed-cadence measurement has a different requirement. Its design needs a result-transfer path that can keep up, such as a qualified DMA arrangement, and a defined policy for overload. Disabling auto-delay alone does not create storage capacity or guarantee lossless acquisition; it changes the failure mode and requires separate overrun analysis.
Clearing EOC without saving the result is not a lossless shortcut. It releases the conversion gate while abandoning the application’s retention obligation. If deliberate discard is acceptable, record it explicitly; otherwise preserve the sample before releasing the gate.
These choices can be summarized without changing the ADC’s documented rule:
| Required behavior | Acceptance evidence |
|---|---|
| Preserve each obtained result, variable cadence allowed | Every admitted conversion is consumed; skipped opportunities are visible |
| Obtain one sample per periodic trigger | Worst-case completion and consumption fit before the next trigger |
| Deliberately discard under overload | Discards are identified; downstream timing assumptions remain valid |
Observe without accidentally releasing the gate
A debugger or diagnostic routine that reads ADC_DR performs the same register access that can end the automatic delay. Disable unsolicited live reads of that register during a proposed delayed-consumer test. This is a control on the experiment, not a claim that a specific debugger was observed causing a failure.
Capture trigger opportunities independently of result reads, and use a single owner for each result. Test a prompt read, a read delayed across two triggers, and a read clearly before the following trigger. Avoid exact-edge coincidence for the explanatory fixture; qualification of boundary timing requires real hardware evidence.
No conversions or firmware builds were executed here. The acceptance record should show which triggers were admitted, which were ignored, and when each returned sample was acquired. That answers the actual auto-delay question without confusing missing acquisitions with analog settling or oversampling arithmetic.
