STM32H563 Mixed I3C Buses: Qualify Legacy I2C Targets Before Reusing the Wiring

An STM32H563 I3C controller can communicate with suitable legacy I2C targets, but reusing a two-wire harness is not enough to establish compatibility. The admission decision depends on target behavior, address allocation and the timing of both legacy and I3C transfers.

This guide uses AN5879 Rev 6, June 2026 and RM0481 Rev 5, chapter 55. Chapter 55 explicitly covers H563. Chapter 54 describes a different implementation for H543/H553, so its target-side static-I2C capability must not be transferred to H563 by analogy. Here, H563 is the controller; the legacy sensors are external targets.

Reject unsupported target behavior first

AN5879 section 8.11 excludes legacy-target clock stretching and 10-bit addressing on the mixed bus. RM0481 section 55.1 likewise permits legacy Standard-mode, Fast-mode and Fast-mode Plus traffic only when the target does not stretch the clock.

Audit the exact commands used by each existing driver. A device that stretches only while a conversion is busy is still incompatible with that command sequence. If its own datasheet documents a no-stretch operating mode, review that mode’s complete readiness and error contract before admitting it. A controller timeout increase does not turn stretching into an allowed mixed-bus behavior.

For each target, record its actual seven-bit address, selected operating mode, clock limits, spike-filter support and the evidence for each item. An unknown entry remains unqualified. A working identity-register read at startup does not exercise every command or busy condition.

Also include level translators, bus buffers and other components in the electrical review. I3C uses push-pull as well as open-drain phases. A board path qualified only for open-drain I2C needs a separate compatibility check before it carries those phases.

Keep legacy addresses separate from I3C discovery

A legacy I2C sensor keeps its static address. It does not gain dynamic-address participation merely because the controller can issue ENTDAA. Build the controller’s address plan from the known legacy population before assigning I3C addresses.

For I3C targets, use the initialization route supported by their documented capabilities. RM0481 Table 613 lists controller support for ENTDAA, SETAASA and SETDASA. Those commands are not interchangeable discovery operations for arbitrary I2C devices. In particular, a command that assigns an I3C target’s dynamic address from a static address does not rewrite a legacy sensor’s fixed address.

Reserve every legacy address and honor the I3C reserved and conditional address restrictions. Then maintain the resulting I3C identity-to-dynamic-address mapping for subsequent private transfers. Reconstruct it when the chosen reset or reinitialization flow invalidates the dynamic addresses. A driver that continues using a remembered address after such a transition can talk to the wrong target or no target at all.

AN5879 section 9.10 gives an H503-board mixed-bus example involving a legacy LIS2DW12. It demonstrates separate I3C address assignment and legacy access; it is not a tested H563 board configuration or a universal target list.

Derive two kinds of timing from the real clock tree

The 50 ns spike-filter distinction matters because a legacy target must not interpret the faster I3C activity as ordinary I2C clocking. AN5879 separates mixed-fast buses containing appropriately filtered targets from mixed-slow cases where a missing filter restricts operation to the slowest legacy device and may remove I3C features. Filter presence does not by itself approve every bus frequency or waveform.

RM0481’s I3C_TIMINGR0 provides separate fields for legacy-I2C SCL high time, open-drain low time, I3C high time and push-pull low time. In the documented filtered mixed-bus case, the I3C high-time constraint is 32 ns to 45 ns. This is a phase timing requirement, not the legacy sensor’s transaction frequency.

Derive the register settings from the actual I3C kernel clock and the selected target requirements. Review the APB and kernel-clock constraints in section 55.6.2 as well. Copying the application note’s H503 example register value into a different H563 clock tree changes the physical durations even when the hex value looks familiar.

If the inventory contains a target with no suitable filter, do not retain the fast mixed-bus timing by default. Establish a documented slower configuration and its feature limits, or keep that target on a separate conventional I2C bus.

Qualify the combination, not only each endpoint

A proposed acceptance sequence begins with each admitted legacy target in the selected no-stretch mode. Add the I3C targets, run the chosen address initialization, and verify both the assigned I3C addresses and unchanged legacy addresses.

Then interleave the intended I3C and legacy transactions while observing SDA and SCL with appropriate equipment. Exercise conversion-busy cases, restart and reinitialization. Confirm that legacy devices remain quiet during traffic not addressed to them and that drivers resume with the current address mapping.

No bus captures or firmware build were performed here. Release the mixed bus only when the inventory, address plan, timing calculations and actual electrical path agree. If one target fails that admission check, retaining a separate I2C segment is a concrete architectural option; a successful transaction with another sensor does not qualify the failing one.