STM32F401CCU6 I2S Slave Startup: Qualify Word Select Before Enabling a Running Stream
An STM32F401CCU6 can transfer audio words while remaining incorrectly synchronized with an external I2S master. One documented cause is enabling the slave during the wrong word-select level after the master has already started clocking. Successful buffer movement alone does not establish a correctly aligned stream.
ES0222 Rev 9, February 2025, section 2.11.6 describes this limitation for STM32F401xB/xC. Its applicability table marks revisions A, 1 and Z affected. The workaround depends on the selected audio format, so a generic instruction to “wait for word select low” is insufficient.
Identify the actual incoming timing signals
For a concrete half-duplex I2S2 design, DS9716 Rev 11, Table 8 lists PB12 as an I2S2_WS option, PB13 as I2S2_CK, and PB15 as I2S2_SD. Confirm the chosen alternate functions and board connections before interpreting a capture. Those names identify one supported pin arrangement, not every possible routing.
In slave mode, the external master supplies clock and word select. RM0368 Rev 6, section 20.4.6 describes those signals as inputs. Changing the slave’s nominal audio-clock calculation cannot repair a wrong relationship between its enable point and the already-running master’s word-select phase.
Record the exact format in SPI_I2SCFGR.I2SSTD, data width and channel length. The I2S Philips format and the MSB- or LSB-justified formats use different relationships between word select and data. The startup condition must be interpreted with that configured format, not with an analyzer’s default decoder.
Apply the two opposite word-select conditions
The erratum states that, with the master already sending clock, enabling the slave while WS is low for I2S, or high for either justified format, can start communication immediately and leave master and slave desynchronized throughout the communication.
Its workaround is explicit:
| Selected format | Word-select level when enabling the slave |
|---|---|
| I2S Philips | WS = high |
| MSB-justified | WS = low |
| LSB-justified | WS = low |
These are startup qualifications for the named formats. They are not a claim that the same rule applies to PCM, nor an instruction to reverse the configured channel polarity. Keep the peripheral’s normal protocol configuration consistent with the external device.
The persistent nature of the described desynchronization matters. Discarding one received word or waiting for another DMA completion is not established by this erratum as a recovery method. Do not treat a later filled buffer as proof that the initial framing defect repaired itself.
Qualify the interval between observing and enabling
A software read showing the required WS level is an observation at that instant. The write that sets SPI_I2SCFGR.I2SE happens later. If word select changes between them, the observation did not establish the level at enable.
Therefore a polling loop is not automatically a race-free implementation of the workaround. Assess the master’s phase duration, the actual observation path, interrupt interference and the time to the enable write. Preserve enough timing margin for the selected implementation; this article supplies no universal instruction-count or microsecond allowance.
Where the system controls both ends, coordinate startup so the slave is prepared before the master begins communication. Where the master must remain running, the integration needs an enable procedure whose phase relationship is justified on the actual target. A source-level condition alone is weaker evidence than a qualified transition.
Keep the normal slave-transmit startup contract
The reference manual’s slave-transmission sequence calls for enabling the slave and loading its first data before the external master begins. For the I2S and justified modes, that first data item belongs to the left channel. It also requires writing I2SE at least two peripheral-clock cycles before the master’s first clock reaches CK.
That two-cycle condition belongs to the documented slave-transmit startup sequence. It is not a general promise that two cycles of software polling safely attach any receive or transmit stream to a running master. Apply the erratum’s word-select condition alongside the relevant normal startup requirements.
After alignment, the data path must still service transfers correctly. Wrong initial phase, transmit starvation and incorrect sample packing are different failure mechanisms. Increasing DMA buffer depth can address neither an unsupported startup assumption nor a mismatched audio format by itself.
Check channel identity with an asymmetric fixture
A proposed isolated test should use distinguishable left and right patterns rather than identical silence. Capture CK, WS and SD, together with a suitable indication of the enable operation. Record how accurately that indication represents the register write; an instrumentation marker is not automatically simultaneous with it.
Compare the first complete words and subsequent channel associations with the selected protocol. Repeat the intended startup path under the system’s permitted scheduling load. Keep underrun or overrun evidence separate from framing observations, and do not assume every desynchronization appears as a simple left/right swap.
No audio stream, register write or timing measurement was performed here. The acceptance result should explain the word-select level at enable, the startup margin and the resulting channel identity. That evidence is stronger than an interrupt count or a claim that audio DMA completed.
