Source-Terminated Gateway Clocks: Why the Driver-Side Half Step Is Not a Logic Fault
A gateway board can show an alarming two-step clock waveform beside its driver and a clean transition at the receiving chip. Replacing the series resistor with a short may make the first trace look more familiar while increasing overshoot at the actual receiver. The engineering question is not whether every point on the trace immediately reaches the supply rail. It is whether the intended receiver gets one valid transition within its electrical and timing limits.