A Linux I2C mux transaction has a route-selection phase, a target transfer, and an optional deselection phase. The locking model determines which other transfers may occur between those phases. Review that exact model and the complete upstream topology before adding a lock: an extra parent-adapter acquisition can deadlock a mux callback, while a missing topology…
A higher sensor FIFO watermark reduces service frequency by letting more samples accumulate, but it also makes the oldest delivered sample older and leaves fewer slots for scheduling delays. Choose the watermark from both an age budget and an occupancy budget. Then verify that the real drain sequence removes complete samples faster than they arrive….
A sensor timestamp is meaningful only when it names the event being timed. Conversion start, conversion completion, interrupt handling, bus-read completion, and userspace receipt can all occur at different instants. Establish the physical sampling event first, then trace how the driver attaches a clock reading to that sample. Applicability: the concrete converter reference is Analog…
Build the IIO scan layout from enabled-channel metadata, then decode each field using its own storage width, byte order, shift, and signedness. A packed C structure or a list sorted by channel name can produce believable values while reading padding or the wrong channel. Applicability: this article pins Linux v6.12. The original Python 3 example…
A reading that improves when sampling slows suggests a timing-dependent error, but it does not identify which timing interval is responsible. Separate the ADC’s acquisition window from the period between conversions, then vary each independently. This distinguishes insufficient input settling from recovery between samples and from unrelated scheduling effects. Applicability: the named hardware reference is…
Define three representations before sending a non-byte SPI frame: the numerical word, its bytes in host memory, and its bits on the wire. A correct value in a debugger does not prove that a byte-oriented wrapper, transfer length, or controller word-width setting will produce the intended clocks. Applicability: this procedure uses the Linux v6.12 SPI…
Map transmitted and received bits on the same clock timeline. SPI clocks both directions, but the peripheral protocol decides which received bits have meaning. Discarding “all command bytes” can lose valid response bits when command and response fields share a host byte. Applicability: the concrete example is Microchip MCP3008 using the three eight-bit-segment framing in…
Translate the peripheral timing diagram into idle level, launch edge, and sample edge before changing SPI frequency. A clock rate reduction cannot make an incorrect edge contract correct. It may only make an accidental timing margin look reliable enough to hide the defect. Applicability: the concrete device is Analog Devices ADXL345 in four-wire SPI, datasheet…
A smaller I2C pull-up resistor improves a passive RC rise time while increasing the current every low-driving device must sink. Select a resistance interval that satisfies both constraints, including tolerances, and then verify it on the populated bus. A cleaner rising edge alone is not sufficient evidence that the change is safe. Applicability: this method…
A low SCL interval can be a permitted peripheral wait or an expired host limit. Establish both contracts: how the selected device signals “not ready,” and whether the controller actually observes SCL and waits long enough. A valid sensor behavior and a valid controller implementation can still be incompatible when their timing policies differ. Applicability:…